This application claims priority to Korean Patent Application No. 2005-74254, filed on Aug. 12, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to temperature sensing, and more particularly, to using multiple temperature detectors having positive and negative delay changes with respect to temperature for more accurately sensing a target temperature.
2. Description of the Related Art
In a dynamic random access memory (DRAM) device, data is stored by charge accumulation in a capacitor of a memory cell. However, leakage current through a PN junction of a MOS transistor reduces such charge accumulation potentially resulting in data loss. Accordingly, a refresh operation is performed for restoring the charge accumulation.
The leakage current in a DRAM memory cell generally increases with temperature. Accordingly, a refresh period is determined based on current leakage at high temperature, but such refresh period is also used at low temperatures resulting in unnecessary current consumption.
Alternatively, the refresh period is adjusted according to temperature for preventing unnecessary current consumption. To that end, a DRAM device includes a temperature sensing circuit for adjusting such a refresh period with temperature.
A temperature sensing circuit with a conventional band gap reference circuit has been widely used. However, this circuit is not used for low power applications due to the presence of a threshold voltage of a diode and a cascode type current mirror.
In particular, a diode is difficult to design for good characteristic in a CMOS process. If trimming points are used for a temperature sensing circuit sensing for a plurality of temperatures, i.e., multi-trimming points, a large resistor, a current mirror, a comparator, and the like are required resulting in difficult implementation.
To solve these problems, a conventional temperature sensing circuit has been implemented with inverter delay chains, as is now described in reference to the accompanying drawings. FIG. 1 shows a block diagram of such a conventional temperature sensing circuit used in a semiconductor memory device.
Referring to FIG. 1, the temperature sensing circuit includes a pulse generator 2, a comparator 4, and a detector 6. The pulse generator 2 receives a self refresh request signal srefreq to generate an active signal active. The comparator 4 receives the active signal active from the pulse generator 2 to generate control signals act and actb and delay signals in1 and in2. The detector 6 receives the control signals act and actb and the delay signals in1 and in2 to generate a temperature sensing signal temp_det.
FIG. 2 shows a circuit diagram of the comparator 4 of FIG. 1. Referring to FIG. 2, the comparator 4 receives the active signal active from the pulse generator 2. The active signal active is delayed through a first delay path 21 to generate delay signal in1 and through a second delay path 23 to generate delay signal in2. Each of the first delay path 21 and the second delay path 23 is implemented with a respective inverter delay chain, as illustrated in FIG. 2. The comparator 4 of FIG. 2 also includes a control circuit 25 that generates the control signals act and actb from the delay signal in1 and the active signal active.
The detector 6 activates the temperature sensing signal temp_det at a target temperature based on the delay signals in1 and in2. Such a temperature sensing signal temp_det is used for adjusting a self refresh period of a semiconductor memory device according to temperature.
FIG. 3 shows graphs of delay amount versus temperature for the delay paths 21 and 23 of FIG. 2. Referring to FIG. 3, three graphs PV1, PV2 and PV3 are such delay characteristics with process variations in fabrication of one of the delay paths 21 or 23. The three graphs PV1, PV2 and PV3 have a substantially same slope but have different off-sets.
Further referring to FIG. 3, the other graph 30 is a delay characteristic for the other of the inverters 21 or 23. The three graphs PV1, PV2 and PV3 and the graph 30 intersect each other at points CP1, CP2 and CP3. Temperatures at such points CP1, CP2 and CP3 are the target temperatures sensed by the temperature sensing circuit with fabrication process variation.
FIG. 3 illustrates that such sensed target temperature varies widely with fabrication process variation such that a target temperature may not be sensed accurately in the prior art.